//~ `New testbench
`timescale  1ns / 1ps

module tb_SOC_top;   

// SOC_top Parameters
parameter PERIOD  = 10;


// SOC_top Inputs
reg   clk                                  = 1 ;
reg   rst_n                                = 0 ;
reg   [2:0]  data_addr                     = 0 ;
reg   data_write_en                        = 0 ;
reg   data_read_en                         = 0 ;
reg   [127:0]  data_write_data             = 0 ;

// SOC_top Outputs
wire  [127:0]  data_read_data              ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

SOC_top  u_SOC_top (
    .clk                     ( clk                      ),
    .rst_n                   ( rst_n                    ),
    .data_addr               ( data_addr        [2:0]   ),
    .data_write_en           ( data_write_en            ),
    .data_read_en            ( data_read_en             ),
    .data_write_data         ( data_write_data  [127:0] ),

    .data_read_data          ( data_read_data   [127:0] )
);

initial
begin
    #(PERIOD*2+6);

    // data_addr = 3'd2; // intxt
    // data_write_en = 1;
    // data_write_data = 128'h00112233445566778899AABBCCDDEEFF;

    // #(PERIOD);

    data_addr = 3'd3; // key
    data_write_en = 1;
    data_write_data = 128'hAABBCCDDEEFF00112233445566778899;
    #(PERIOD);

    data_addr = 3'd1;
    data_write_data = 1;
    data_write_data = {120'd0,8'b01100000};
    #(PERIOD);

    data_write_en = 0;
    #(PERIOD);

    data_addr = 3'd1;
    data_write_data = 1;
    data_write_data = {120'd0,8'b01010000};
    #(PERIOD);
    data_write_en = 0;


    @(posedge u_SOC_top.u_address_map.keyexprdy);
    #(PERIOD*10);

    $stop;
end

endmodule